Researchers have created accurate software models of AMD matrix cores

A group of researchers developed high-precision software models for matrix multipliers used in AMD CDNA architectures of the 1st, 2nd, and 3rd generations. The project is aimed at ensuring full software emulation of hardware calculations, which is critical for debugging and optimizing high-performance computing.

During the work, the authors achieved bit-accurate reproducibility of results, which means complete coincidence of the software model calculations with the real hardware. To confirm the correctness of the algorithms, the researchers used an array of 10 million random test vectors, running them through hardware blocks and software emulators.

The development process included an iterative refinement method, which allowed for the elimination of discrepancies in floating-point operations and specific instructions of matrix cores. The resulting models enable AI and scientific computing software developers to conduct in-depth performance analysis without the need for constant access to physical AMD Instinct series accelerators.

This study significantly simplifies the code verification process for CDNA architectures. The ability to accurately model at the bit level allows for the detection of errors in compilers and linear algebra libraries at early stages of development, reducing testing time and increasing the reliability of calculations in large clusters.