FEX developers revealed the complexities of emulating x86 on the ARM architecture

The team behind the FEX project has published a detailed technical report on the challenges of translating x86 instructions for ARM architecture processors. The main obstacle was the fundamental difference in memory models: x86 uses a strict Total Store Ordering (TSO) model, while ARM relies on a weakly ordered operation model.

In the process of emulation, developers encountered the need for precise handling of atomic instructions, which require execution order guarantees not provided by the native ARM architecture. Particular attention is paid to split-locks - situations where an atomic operation affects data that crosses cache line boundaries. This leads to significant delays, as it requires locking the memory bus to ensure data integrity.

The study also covers working with uncached memory, where the lack of caching makes write operations extremely slow. To overcome these limitations, engineers have to implement complex software memory barriers, which reduce the overall performance of the emulator. The document provides a detailed breakdown of the mechanisms by which FEX attempts to minimize overhead when translating code in real-time.

Understanding these low-level limitations is critical for the development of cross-platform software. Solving memory synchronization problems directly affects the speed of applications running through emulators on modern ARM processors, including server solutions and mobile chips.